| 主权项 |
1. A method for conversion of a value of an analog signal to a compressed digital word using a conversion of the analog signal to a linear digital word according to a successive approximation scheme, while a number of bits of the linear digital word is not lower than m, and at the same time, the number of bits of the linear digital word is higher than a number of bits of a compressed digital word, and the number of bits of the compressed digital word is not lower than n, whereas the bits of the linear digital word are already evaluated by the use of a linear analog-to-digital converter and provided to a linear digital input, wherein the conversion of a value of the analog signal to the linear digital word (LW) is terminated by the use of a compression module (CPM) when all bits of the compression word (CW) are already evaluated, while a compression starts when the compression module (CPM) detects an active state on a compression trigger input (TrgCP), and then a number equal to a difference between numbers m and v is written to a section number register (RegS) in the compression module (CPM), while v is an arbitrarily chosen natural number smaller than n, and after detection, on the basis of a bit ready signal (BitRdy), that a new output bit in the linear digital word (LW) has been evaluated by the linear analog-to-digital converter (SA-ADC), a content of the section number register (RegS) is decreased by one if a state of the new output bit in the linear digital word (LW) has been evaluated to zero, while the content of the section number register (RegS) is not decreased if a state of the new output bit in the linear digital word (LW) has been evaluated to one, or if the content of the section number register (RegS) has been already reduced to zero, and then, in both cases, the evaluation of next v bits of the linear digital word (LW) by the linear analog-to-digital converter (SA-ADC) is awaited, and a number of v occurrences of a bit ready signal (BitRdy) is counted, and afterwards, a complete conversion signal (End) is generated by the compression module (CPM), which terminates the conversion of the analog signal to the linear digital word (LW), and introduces the linear analog-to-digital converter (SA-ADC) to a stand by state, while the states of v bits of the linear digital word (LW) evaluated recently are assigned by the compression module CPM respectively to the least significant v bites of the compressed word (CW), and the content of the section number register (RegS) is written by the compression module CPM to the more significant bites of the compressed word (CW). |
