发明名称 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
摘要 A semiconductor memory device according to an embodiment includes a memory cell array that includes memory cells and a plurality of first conducting layers. The memory cells are arrayed in a three-dimensional manner. The first conducting layers are connected to the memory cells and are arrayed in a laminating direction. Stepped wiring portion includes a plurality of second conducting layers. The plurality of second conducting layers connect the first conducting layers and external circuits. At least one of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the stepped wiring portion positioned on the first side portion side. Other ones of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the stepped wiring portion positioned on the second side portion side.
申请公布号 US2017077139(A1) 申请公布日期 2017.03.16
申请号 US201615255786 申请日期 2016.09.02
申请人 Kabushiki Kaisha Toshiba 发明人 IGUCHI Tadashi
分类号 H01L27/115;H01L23/50;H01L21/48;H01L23/498 主分类号 H01L27/115
代理机构 代理人
主权项 1. A semiconductor memory device, comprising: a memory cell array that includes a plurality of memory cells and a plurality of first conducting layers, the memory cells being arrayed in a three-dimensional manner, the first conducting layers being connected to the memory cells and being arrayed in a laminating direction; and stepped wiring portions disposed on a first side portion of the memory cell array and a second side portion thereof, the second side portion being different from the first side portion, the stepped wiring portion including a plurality of second conducting layers, the plurality of second conducting layers being connected to the first conducting layers, wherein at least one of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the stepped wiring portion positioned on the first side portion side, and other ones of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the stepped wiring portion positioned on the second side portion side.
地址 Minato-ku JP