发明名称 半導体集積回路装置
摘要 Provided is a constant voltage circuit having a stable output voltage. In a constant voltage circuit formed by connecting an enhancement type NMOS and a depression type NMOS in series, in order to enhance the back bias effect of the depression type NMOS, the impurity concentration is set to be high only in a P-type well region on which the depression type NMOS is arranged.
申请公布号 JP6095927(B2) 申请公布日期 2017.03.15
申请号 JP20120215034 申请日期 2012.09.27
申请人 エスアイアイ・セミコンダクタ株式会社 发明人 原田 博文;橋谷 雅幸
分类号 H01L21/8234;H01L21/822;H01L27/04;H01L27/088 主分类号 H01L21/8234
代理机构 代理人
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