Scheme for masking output of scan chains in test circuit

摘要

A method for masking scan chains in a test circuit of an integrated circuit is disclosed. A test pattern to be fed into the test circuit of the integrated circuit is generated. The generated test pattern can be used for detecting a primary fault, one or more secondary faults, and one or more tertiary faults. A mask to mask the output of the scan chains of the test circuit is generated. If a condition is not met, a mask that increases the total number of detectable faults is generated. If the condition is met, a mask that protects the primary fault of the test pattern is generated.

主权项

1. A computer implemented method for masking scan chains in a test circuit of an integrated circuit, the method comprising:
generating, by a computer, a test pattern including a plurality of input values for detecting a primary fault representing a fault for which an initial subset of input values in the test pattern is generated, at least one secondary fault representing a fault detectable by specifying input values other than the initial subset of input values, and at least one tertiary fault representing a fault detectable by the test pattern specified with the input values for the primary and the at least one secondary fault; responsive to a condition not being met, generating first mask data configured to mask a first subset of scan chains to increase a total number of detectable primary, secondary, and tertiary faults associated with the test pattern; and responsive to the condition being met, generating second mask data configured to mask a second subset of scan chains to protect the primary fault associated with the test pattern.