发明名称 |
Apparatuses and methods for performing logical operations using sensing circuitry |
摘要 |
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access. |
申请公布号 |
US9589607(B2) |
申请公布日期 |
2017.03.07 |
申请号 |
US201615051112 |
申请日期 |
2016.02.23 |
申请人 |
Micron Technology, Inc. |
发明人 |
Manning Troy A. |
分类号 |
G11C7/06;G06F3/06;G11C7/10;G06F12/00;G11C7/22;G11C11/4074;G11C11/4091;G06F7/523;H03K19/00 |
主分类号 |
G11C7/06 |
代理机构 |
Brooks, Cameron & Huebsch, PLLC |
代理人 |
Brooks, Cameron & Huebsch, PLLC |
主权项 |
1. An apparatus, comprising:
an array of memory cells; sensing circuitry comprising:
a first latch coupled to a sense line of the array; anda second latch coupled to the first latch; and a controller configured to control accumulating, in the second latch, a result of a first operation phase of a logical operation and a number of intermediate operation phases of the logical operation; wherein the first operation phase comprises sensing a memory cell coupled to the sense line; wherein the number of intermediate operation phases comprise sensing a respective number of different memory cells coupled to the sense line; and wherein an accumulated result in the second latch is a result of the logical operation. |
地址 |
Boise ID US |