Handling maximum activation count limit and target row refresh in DDR4 SDRAM

摘要

Efficiently tracking activations to rows of memory using a reduced number of row activation counters that indicate whether a memory row is activated during an activation period and row activation counters that indicate a number of permitted activations to a memory row within a maximum activation window.

主权项

1. A memory controller for controlling a memory, the memory controller comprising:
a page table configured to store using a first table and a second table, wherein:
the first table includes a first entry, the first entry comprising:
a first identifier that identifies a first memory row of the memory activated during a first period of time; anda first timeout counter that indicates a first time remaining during the first period of time, andthe second table includes a second entry, the second entry comprising:
a second identifier that identifies a second memory row of the memory activated during at least one second period of time;an activation counter that counts a quantity of activations of the second memory row; anda second timeout counter that indicates a second time remaining during the at least one second period of time.