Memory device check bit read mode

摘要

A check bit read mode enables a memory device to provide internal check bits to an associated host. A memory controller of a memory subsystem can generate one or more read commands for memory devices of the memory subsystem. The read command can include address location information. The memory devices include memory arrays with memory locations addressable with the address location information. The memory locations have associated data and internal check bits, where the check bits are generated internally by the memory for error correction. If the memory device is configured for check bit read mode, in response to the read command, it sends the internal check bits associated with the identified address location. If the memory device is not configured check bit read mode, it returns the data in response to the read command without exposing the internal check bits.

主权项

1. A dynamic random access memory device (DRAM), comprising:
a memory array including memory locations addressable with address information, the memory locations including data and internal check bits associated with the data, the DRAM to generate the internal check bits during an error checking operation; and I/O (input/output) circuitry to couple to an associated memory controller, the I/O circuitry to receive a read command when coupled to the associated memory controller, the read command to identify an address location; wherein in response to the read command, if the DRAM is configured for a check bit read (CBRD) mode, the read command to cause the DRAM to send internal check bits associated with the identified address location via the I/O circuitry, and if the DRAM is not configured for the CBRD mode, the read command to cause the DRAM to return data associated with the identified address location without exposing the internal check bits.