发明名称 |
PHOTO PATTERN METHOD TO INCREASE VIA ETCHING RATE |
摘要 |
Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided. |
申请公布号 |
US2017062270(A1) |
申请公布日期 |
2017.03.02 |
申请号 |
US201615351774 |
申请日期 |
2016.11.15 |
申请人 |
MACRONIX INTERNATIONAL CO., LTD. |
发明人 |
MU Zheng-Chang;LIN Cheng-Wei;LIU Kuang-Wen |
分类号 |
H01L21/768;H01L21/321;H01L21/311 |
主分类号 |
H01L21/768 |
代理机构 |
|
代理人 |
|
主权项 |
1. A method of fabricating a semiconductor device having a via, the method comprising:
forming an inter-metal dielectric layer on a first portion of a conductive bottom substrate layer, wherein the first portion of the conductive bottom substrate layer is isolated from surrounding portions of the conductive bottom substrate layer; photo patterning a via mask onto the inter-metal dielectric layer; etching the inter-metal dielectric layer to define an open via area to the first portion of the conductive bottom substrate layer, wherein a portion of the inter-metal dielectric layer remains around the open via area with the first portion of the conductive bottom there below; depositing a conductive via material in the open via area adjacent the first portion of the conductive bottom substrate layer; removing conductive via material remaining above the inter-metal dielectric layer; and forming a conductive top layer on the inter-metal dielectric layer and the conductive via material, wherein photo patterning the via mask onto the inter-metal dielectric layer comprises photo patterning the via mask with a via area mask open ratio of at least 90%. |
地址 |
Hsin-Chu TW |