发明名称 MULTI-LEVEL FLASH STORAGE DEVICE WITH MINIMAL READ LATENCY
摘要 A memory system, non-volatile solid-state memory, and a method of efficiently reading data from a flash memory array are disclosed. The disclosed memory system includes a flash memory array having a plurality of memory cells that store data therein, each of the plurality of memory cells being configured to store at least two bits per cell and being organized into pages, and a controller configured to read any bit of data from a page of the flash memory array by applying a single threshold voltage to the flash memory array. Reading data from the flash memory array with a single threshold greatly decreases the latency associated with the read operation.
申请公布号 US2017062045(A1) 申请公布日期 2017.03.02
申请号 US201514839535 申请日期 2015.08.28
申请人 Avago Technologies General IP (Singapore) Pte. Ltd. 发明人 Wilson Bruce Alexander
分类号 G11C11/56 主分类号 G11C11/56
代理机构 代理人
主权项 1. A memory system, comprising: a flash memory array having a plurality of memory cells that store data therein, each of the plurality of memory cells being configured to store more than one bit per cell and being organized into pages on different media of the flash memory array; and a controller configured to read a page of a selected one of the different media by applying a single threshold voltage to the flash memory array, wherein a combination of at least two of the plurality of memory cells is assigned to one of multiple possible states to store the data, and wherein the controller reads the data with the single threshold that corresponds to one of multiple possible thresholds associated with the multiple possible states.
地址 Singapore SG