Performance of processors is improved by limiting number of branch prediction levels

摘要

A method utilizes information provided by performance monitoring hardware to dynamically adjust the number of levels of speculative branch predictions allowed (typically 3 or 4 per thread) for a processor core. The information includes cycles-per-instruction (CPI) for the processor core and number of memory accesses per unit time. If the CPI is below a CPI threshold; and the number of memory accesses (NMA) per unit time is above a prescribed threshold, the number of levels of speculative branch predictions is reduced per thread for the processor core. Likewise, the number of levels of speculative branch predictions could be increased, from a low level to maximum allowed, if the CPI threshold is exceeded or the number of memory accesses per unit time is below the prescribed threshold.

主权项

1. A method comprising
providing a computer system that includes a processor having at least one processor core and a predefined number of speculative branches; providing a memory coupled to said computer system wherein said memory includes a memory interface; determining a number of accesses made to said memory in a specified time interval; and adjusting the predefined number of speculative branches based on the number of accesses made to said memory in the specified time interval wherein performance of the processor is enhanced when the predefined number of speculative branches is adjusted based on the number of accesses made to said memory in the specified time interval.