| 发明名称 | Semiconductor memory device and testing method thereof | ||
| 摘要 | A semiconductor memory device is provided which includes memory cells, a first error correction code (ECC) circuit configured to generate at least one selected parity bit corresponding to a selected data bit using an error correction code during a write operation and to correct an error of the selected data bit using the selected parity bit during a read operation, and a test circuit configured to selectively perform at least one of an error correction operation and a redundancy repair operation on at least one of the selected data bit and the selected parity bit based on test mode register set (TMRS) information. | ||
| 申请公布号 | US9583215(B2) | 申请公布日期 | 2017.02.28 |
| 申请号 | US201414532392 | 申请日期 | 2014.11.04 |
| 申请人 | SAMSUNG ELECTRONICS CO., LTD. | 发明人 | Jeong Yonghwan;Chung Hoiju |
| 分类号 | G11C29/00;G11C29/42;G06F11/10;G06F11/22;G11C11/40;G11C29/04 | 主分类号 | G11C29/00 |
| 代理机构 | Harness, Dickey & Pierce, P.L.C. | 代理人 | Harness, Dickey & Pierce, P.L.C. |
| 主权项 | 1. A semiconductor memory device comprising: memory cells; a first error correction code (ECC) circuit configured to generate at least one selected parity bit corresponding to a selected data bit using an error correction code during a write operation and to correct an error of the selected data bit using the selected parity bit during a read operation; and a test circuit configured to selectively perform at least one of an error correction operation and a redundancy repair operation on at least one of the selected data bit and the selected parity bit based on test mode register set (TMRS) information. | ||
| 地址 | Gyeonggi-do KR | ||