Chip embedded package method and structure

摘要

A chip embedded package method is provided by an embodiment of the present invention. The method comprises: etching metallic sinks on the thicker metal layer of each organic substrate; part of metallic sinks is used for packaging at least one chip, and other metallic sinks are used for via-holes; mounting the at least one chip into a metallic sink of each organic substrate via adhesive; flipping one organic substrate on another to form a combination; drilling blind-holes on both sides of the combination of the two organic substrates to pass through the adhesive; drilling via-holes to get through the combination of the two organic substrates, wherein the via-holes locates beyond the metallic sinks with chips; filling the blind-holes and via-holes with conductive medium through an electroplating process.

主权项

1. A chip embedded package structure, comprising:
a combination of two organic substrates, wherein, one organic substrate is flipped on the other and each organic substrate comprises:
a corelayer;a metal layer on the corelayer;metallic sinks etched on the metal layer; part of metallic sinks used for packaging at least one chip, and other metallic sinks used for via-holes;the at least one chip mounted into a metallic sink via adhesive; blind-holes on both sides of the combination of the two organic substrates and passing through the adhesive; via-holes, getting through the combination of the two organic substrates, and wherein the via-holes are located beyond the metallic sinks with chips, and at least one of the via-holes is connected with the metal layer; and wherein, the blind-holes and via-holes are filled with conductive medium.