Integrated fin and strap structure for an access transistor of a trench capacitor

摘要

At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the SOI substrate. Selective epitaxy is performed to fill a cavity overlying the inner electrode with an epitaxial semiconductor material portion. A top semiconductor material layer and the epitaxial semiconductor material portion are patterned to form a fin structure including a portion of the top semiconductor material layer and a portion of the epitaxial semiconductor material portion. The epitaxial semiconductor material portion functions as a conductive strap structure between the inner electrode and a semiconductor device to be formed on the fin structure.

主权项

1. A semiconductor structure comprising:
a trench capacitor embedded in a stack of a semiconductor substrate and an insulator layer and comprising an inner electrode, a node dielectric, and an outer electrode; and an integrated fin and strap structure located on said insulator layer and comprising a semiconductor fin and an epitaxial semiconductor strap structure, wherein said epitaxial semiconductor strap structure is epitaxially aligned to said semiconductor fin and extends below a top surface of said insulator layer, wherein said epitaxial semiconductor strap structure includes a non-recessed pillar portion in direct physical contact with a sidewall surface of said semiconductor fin and having a first height, and a recessed pillar portion located under said non-recessed pillar portion and having a second height that is less than the first height, said epitaxial semiconductor strap structure is spaced apart from a topmost surface of said inner electrode by a polycrystalline semiconductor material portion, said polycrystalline semiconductor material portion has a non-uniform vertical thickness and a non-planar top surface and is present on an entirety of said topmost surface of said inner electrode.