METHOD OF FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR

摘要

In one embodiment, a semiconductor device may include forming a first inverter and a second inverter to selectively receive separate inputs of a differential input signal and directly connecting each of the first and second inverters to receive power directly from a voltage input and a voltage return. The first inverter may be configured to include a first control switch that is configured to selectively couple together an upper transistor and a lower transistor of the first inverter. The second inverter may be configured to include a second control switch that is configured to selectively couple together an upper transistor and a lower transistor of the second inverter.

主权项

1. A comparator latch of a semiconductor device comprising:
a first transistor of a first selectively switched inverter having a first current carrying electrode coupled to directly receive a voltage from a voltage supply input of the comparator latch, the first transistor of the first selectively switched inverter having a control electrode coupled to receive a first input signal, the first transistor of the first selectively switched inverter also having a second current carrying electrode; a second transistor of the first selectively switched inverter having a first current carrying electrode coupled to directly receive a voltage from a voltage return input of the comparator latch, the second transistor of the first selectively switched inverter having a control electrode coupled to receive the first input signal, the second transistor of the first selectively switched inverter also having a second current carrying electrode; a first selectively enabled control switch having a first terminal coupled to the second current carrying electrode of the first transistor of the first selectively switched inverter, a second terminal coupled to the second current carrying electrode of the second transistor of the first selectively switched inverter, and a control electrode coupled to receive a first clock signal; a first transistor of a second selectively switched inverter having a first current carrying electrode coupled to directly receive the voltage from the voltage supply input of the comparator latch, the first transistor of the second selectively switched inverter having a control electrode coupled to receive a second input signal that has substantially the same amplitude as the first input signal but has a substantially opposite polarity to the first input signal, the first transistor of the second selectively switched inverter also having a second current carrying electrode; a second transistor of the second selectively switched inverter having a first current carrying electrode coupled to directly receive the voltage from the voltage return input of the comparator latch, the second transistor of the second selectively switched inverter having a control electrode coupled to receive the second input signal, the second transistor of the second selectively switched inverter also having a second current carrying electrode; and a second selectively enabled control switch having a first terminal coupled to the second current carrying electrode of the first transistor of the second selectively switched inverter, a second terminal coupled to the second current carrying electrode of the second transistor of the second selectively switched inverter, and a control electrode coupled to receive the first clock signal.