发明名称 WAFER LEVEL CHIP PACKAGING METHOD
摘要 Provided is a wafer level chip packaging method, comprising: 1) providing a carrier (11), a bonding layer (12) forming on the surface of the carrier; 2) forming a dielectric layer (13) on the surface of the bonding layer; 3) attaching a semiconductor chip (14), with its front face facing downwards, on the surface of the dielectric layer; 4) packaging each semiconductor chip by adopting the injection molding technique; 5) separating the bonding layer from the dielectric layer, so as to remove the carrier and the bonding layer; 6) forming a rewiring layer (16) for the semiconductor chip based on the dielectric layer; and 7) performing a ball reflow process on the rewiring layer, so as to form micro bumps (17). By way of fabricating a dielectric layer between the bonding layer and the semiconductor chip, the problem of the semiconductor chip being contaminated due to the fact that the bonding layer is directly bonded to the semiconductor chip is avoided. By means of the packaging method, the condition whereby the semiconductor chip is contaminated during the process of packaging is largely controlled, thereby improving the rate of finished products and the electrical property of the semiconductor chip.
申请公布号 WO2017024846(A1) 申请公布日期 2017.02.16
申请号 WO2016CN82846 申请日期 2016.05.20
申请人 SJ SEMICONDUCTOR (JIANGYIN) CORPORATION 发明人 LIN, Chengchung;QIU, Yuedong
分类号 H01L23/14;H01L21/56;H01L21/58;H01L21/78;H01L23/29 主分类号 H01L23/14
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