发明名称 |
Frequency synthesizer circuit |
摘要 |
The invention relates to frequency synthesizer circuits, and in particular to frequency synthesizer circuits characterized by a small channel spacing. Embodiments disclosed include a frequency synthesizer circuit for a radio receiver, the circuit comprising: a digitally controlled oscillator configured to generate an output signal with an output frequency on application of an oscillator enable signal; a delay module; configured to delay an input reference signal to generate a delayed reference signal; and a duty cycle module configured to modulate the oscillator enable signal based on a period of an input reference signal and the delay of the delayed reference signal, such that a ratio between the output frequency and the frequency of the input reference signal is a non-integer. |
申请公布号 |
US9571071(B2) |
申请公布日期 |
2017.02.14 |
申请号 |
US201514747143 |
申请日期 |
2015.06.23 |
申请人 |
NXP B.V. |
发明人 |
Saric Tarik;Drago Salvatore |
分类号 |
H03D3/18;H03D3/24;H03K3/03;H03L7/099;H03L7/22;H04B1/16 |
主分类号 |
H03D3/18 |
代理机构 |
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代理人 |
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主权项 |
1. A frequency synthesizer circuit for a radio receiver, the circuit comprising:
a digitally controlled oscillator configured to generate an output signal with an output frequency on application of an oscillator enable signal; a delay module configured to delay an input reference signal to generate a delayed reference signal; a duty cycle module configured to generate the oscillator enable signal based on a period of the input reference signal and the delay of the delayed reference signal such that a ratio between the output frequency and a frequency of the input reference signal is a non-integer; wherein the delay module comprises: a time delay oscillator driven by an oscillator control voltage and configured to delay the delay module input reference signal by an amount based on a number of stages of the time delay oscillator: and wherein the delay module further comprises; a multiplexer with a selectable channel input; and a copy time delay oscillator configured to be controlled by said oscillator control voltage and operable to delay the input reference signal to generate the delayed reference signal. |
地址 |
Eindhoven NL |