| 发明名称 | Data aware write scheme for SRAM | ||
| 摘要 | Approaches for providing write-assist for a Static Random Access Memory (SRAM) array are provided. A circuit includes a control circuit connected to a cell in a SRAM array. The control circuit is configured to: apply a first voltage to a first pull down transistor of the cell during a write operation to the cell; and apply a second voltage, different than the first voltage, to a second pull down transistor of the cell during the write operation. | ||
| 申请公布号 | US9570156(B1) | 申请公布日期 | 2017.02.14 |
| 申请号 | US201514832127 | 申请日期 | 2015.08.21 |
| 申请人 | GLOBALFOUNDRIES INC. | 发明人 | Braceras George M.;Bringivijayaraghavan Venkatraghavan;Chishti Sheikh S. |
| 分类号 | G11C11/00;G11C11/419;G11C5/14;G11C11/412;G11C11/413 | 主分类号 | G11C11/00 |
| 代理机构 | Roberts Mlotkowski Safran Cole & Calderon, P.C. | 代理人 | Canale Anthony;Calderon Andrew M.;Roberts Mlotkowski Safran Cole & Calderon, P.C. |
| 主权项 | 1. A circuit, comprising: a control circuit connected to a cell in a Static Random Access Memory (SRAM) array, wherein the control circuit is configured to: apply a first voltage to a first pull down transistor of the cell during a write operation to the cell; andapply a second voltage, different than the first voltage, to a second pull down transistor of the cell during the write operation,wherein a trigger signal causes the second voltage to be different than the first voltage, the trigger signal being based on a bit-switch signal that controls a bit-switch connected to the cell. | ||
| 地址 | Grand Cayman KY | ||