Analog/digital converter and solid-state imaging device

摘要

An analog/digital converter includes: a ramp signal generation circuit that generates a ramp signal; a comparison circuit that compares potential of an input analog signal with potential of the ramp signal and outputs a comparator output signal if the potential of the ramp signal satisfies the predetermined condition; a count control circuit that divides a predetermined ramp period in which the ramp signal generation circuit outputs the ramp signal into a predetermined number n of divided ramp periods and outputs a count-stop signal; a counter circuit that counts time in the divided ramp period and outputs a count value of the counted time; and a decoder circuit that generates a digital signal according to a count value and a digital value corresponding to any one of the divided ramp periods in which the counter circuit has started counting of time and outputs the generated digital signal.

主权项

1. An analog/digital converter comprising:
a ramp signal generation circuit configured to generate a ramp signal of which potential monotonously changes with time at a certain rate; a comparison circuit configured to compare potential of an input analog signal with potential of the ramp signal, and to output a comparator output signal indicating that a predetermined condition is satisfied if the potential of the ramp signal satisfies the predetermined condition in relation to the potential of the analog signal; a count control circuit configured to divide a predetermined ramp period in which the ramp signal generation circuit outputs the ramp signal into a predetermined number n of divided ramp periods (where n is an integer of 2 or more), and to output a count-stop signal for stopping counting of time in each of the divided ramp periods; a counter circuit configured to count time in the divided ramp period from a time when the comparator output signal is input to a time when the count-stop signal is first input, and to output a count value of the counted time; and a decoder circuit configured to generate a digital signal corresponding to the input analog signal according to a digital value corresponding to the count value and a digital value corresponding to any one of the divided ramp periods in which the counter circuit has started counting of time, and to output the generated digital signal.