SHIFT REGISTER, GATE DRIVING CIRCUIT, DISPLAY PANEL AND DISPLAY APPARATUS

摘要

There are provided a shift register, a gate driving circuit, a display panel and a display apparatus. The shift register comprises: an input module (01) configured to output a signal of a signal input terminal to a first node (P1); a reset module (02) configured to output a signal of a reset signal terminal to the first node (P1); an output module (03) configured to output a signal of the first node (P1) to a scanning signal output terminal (Out); a buffer module (04) configured to output the signal of the first node (P1) to a triggering signal terminal (STV); and an auxiliary module (05) configured to output a high level signal input by the clock signal terminal (CLK) to the second node (P2) which controls the output module (03) to output the scanning signal to the scanning signal output terminal. The shift register inputs selectively the clock signal when the shift register outputs a scanning signal by adding the auxiliary module, such that the power consumption of the shift register can be reduced, and thus the yield rate of display panels is raised.

主权项

1. A shift register, comprising:
an input module, whose input terminal is connected to a signal input terminal, first control terminal is connected to a first reference signal terminal, second control terminal is connected to a second reference signal terminal, and output terminal is connected to a first node, and configured to output a signal of the signal input terminal to the first node under the control of the first reference signal terminal and the second reference signal terminal; a reset module, whose input terminal is connected to a reset signal terminal, first control terminal is connected to the second reference signal terminal, second control terminal is connected to the first reference signal terminal, and output terminal is connected to the first node, and configured to output a signal of the reset signal terminal to the first node under the control of the first reference signal terminal and the second reference signal terminal; an output module, whose input terminal is connected to the first node, control terminal is connected to a second node, and output terminal is connected to a scanning signal output terminal, and configured to output a signal of the first node to the scanning signal output terminal under the control of the second node; a buffer module, whose input terminal is connected to the first node, control terminal is connected to a clock signal terminal, and output terminal is connected to a triggering signal terminal, and configured to output the signal of the first node to the triggering signal terminal for inputting a triggering signal to a signal input terminal of an adjacent next state of shift register under the control of the clock signal terminal; and an auxiliary module, whose first input terminal is connected to the clock signal terminal, second input terminal is connected to a low level signal terminal, first control terminal is connected to the signal input terminal, second control terminal is connected to the reset signal terminal, and output terminal is connected to the second node, and configured to output a high level signal input by the clock signal terminal, under the control of the signal input terminal and the reset signal terminal, to the second node which controls the output module to output a scanning signal to the scanning signal output terminal.