SEMICONDUCTOR DEVICE INCLUDING FIN HAVING CONDENSED CHANNEL REGION

摘要

A finFET semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The semiconductor fin includes a channel region interposed between opposing source/drain regions. A gate stack is on the upper surface of the substrate and wraps around sidewalls and an upper surface of only the channel region. The channel region further includes a condensed portion formed of a first semiconductor material and a second semiconductor material. The source/drain regions are formed of the first semiconductor material while excluding the second semiconductor material.

主权项

1. A method of fabricating a finFET device, the method comprising:
forming, on an upper surface of a semiconductor substrate, at least one semiconductor fin comprising a first semiconductor material, the at least one semiconductor fin having a channel region interposed between opposing source/drain regions; forming first and second opposing gate spacers that wrap around the exterior surface of the at least one fin and define a gate region that extends between the first and second gate spacers to define a total gate region length; forming a flowable insulator layer on the source/drain regions, and forming a dummy gate stack on the channel region; selectively removing the dummy gate stack with respect to the flowable insulator layer to expose the channel region; forming a condenser layer including a donor material directly on an upper surface and sidewalls of the exposed channel region; performing a condensation process to selectively transform the exposed channel region into a second semiconductor material different from the first semiconductor material so as to increase carrier mobility conductivity of the channel region, while maintaining the first semiconductor material of the source/drain regions, wherein the second semiconductor material has a total condensed channel length extending from an inner side of the first gate spacer to an inner side of the second gate spacer that matches the gate region length.