Integrated circuit with power network aware metal fill

摘要

In the physical design of an integrated circuit, comparing metal fill locations with an average least resistance path (LRP) for a cell and then filling the location with either power or ground tiles based on the comparison. For each metal layer, all of the metal fill locations are determined and nearby metal fills, i.e., those within a predetermined radius of a located metal fill are connected. A Design Rule Check (DRC) is performed to ensure that connected metal fills meet design specifications, for example, that connected metal fills are not too close to a signal line. The metal fill method improves the power integrity of the design.

主权项

1. A computer implemented method for forming an integrated circuit (IC), wherein the computer includes a processor and a memory coupled to the process, the method comprising:
(a) receiving and storing in the memory an IC design comprising a functional description of the IC including circuit blocks that have been placed and routed; (b) extracting, by the processor, power and ground networks of the IC design; (c) breaking the IC design up into a predetermined number of regions, by the processor, wherein each region includes a plurality of cells; (d) calculating, by the processor, a least resistance path (LRP) of the power and ground networks for a predetermined number of the cells within each region; (e) determining, by the processor, average LRPs of the power and ground networks for each region of the IC design; (f) filling, by the processor, the cells in said regions with one of power and ground tiles depending on the average LRP of said region, thereby generating a new IC design; and storing the new IC design in the memory and performing a design rules check on the new IC design to ensure that connecting the located power and ground tiles with respective nearby power and ground tiles does not violate predetermined design rules.