发明名称 |
CLASS-D AMPLIFIER CIRCUITS |
摘要 |
Methods and apparatus for Class-D amplifier circuits with improved power efficiency. The circuit has an output stage with at least first and second switches and a modulator that receives an input signal to be amplified, SIN, and a first clock signal fSW. The modulator controls the duty cycles of the first and second switches, within a switching cycle based on the input signal, wherein the switching cycle has a switching frequency based on the first clock signal. A frequency controller controls the frequency of the first clock signal in response to an indication of the amplitude of the input signal so as to provide a first switching frequency at a first input signal amplitude and a second, lower, switching frequency at a second, lower, input signal amplitude. A lower switching frequency can be tolerated at low signal amplitudes and varying the switching frequency in this way thus maintains stability whilst reducing switching power losses. |
申请公布号 |
US2017019079(A1) |
申请公布日期 |
2017.01.19 |
申请号 |
US201615278862 |
申请日期 |
2016.09.28 |
申请人 |
Cirrus Logic International Semiconductor Ltd. |
发明人 |
Lesso John P.;Ido Toru |
分类号 |
H03F3/217;H03G1/00;H03F3/187 |
主分类号 |
H03F3/217 |
代理机构 |
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代理人 |
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主权项 |
1. A Class-D amplifier circuit for amplifying an input signal comprising:
an output stage comprising at least first and second switches; a modulator comprising a signal input for receiving said input signal and a clock input for receiving a first clock signal, the modulator being configured to generate a switch control signal to control the duty cycles of said first and second switches within a switching cycle based on said input signal, wherein said switching cycle has a switching frequency based on said first clock signal; and a frequency controller configured to control the frequency of said first clock signal based on said switch control signal. |
地址 |
Edinburgh GB |