发明名称 |
METHOD FOR MANUFACTURING A NONVOLATILE MEMORY DEVICE |
摘要 |
A method for manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention may include providing a substrate comprising a cell region and a peripheral region, wherein the peripheral region comprises an NMOS region and a PMOS region; performing a well forming ion implantation over the substrate in the cell region and the NMOS region; performing a threshold voltage adjusting ion implantation over a surface of the substrate in the cell region and the NMOS region; forming a gate pattern comprising a floating gate electrode in the cell region and the peripheral region; and performing a junction ion implantation over a surface of the cell region, wherein the floating gate electrode may have P-type conductivity. |
申请公布号 |
US2017018559(A1) |
申请公布日期 |
2017.01.19 |
申请号 |
US201514943680 |
申请日期 |
2015.11.17 |
申请人 |
SK hynix Inc. |
发明人 |
KIM Do-Young |
分类号 |
H01L27/115;H01L21/265;H01L29/788;H01L29/36;H01L29/423;H01L29/66;H01L21/28 |
主分类号 |
H01L27/115 |
代理机构 |
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代理人 |
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主权项 |
1. A method for manufacturing a nonvolatile memory device comprising:
providing a substrate comprising a cell region and a peripheral region, wherein the peripheral region comprises an NMOS region and a PMOS region; performing a well forming ion implantation over the substrate in the cell region and the NMOS region; performing a threshold voltage adjusting ion implantation over a surface of the substrate in the cell region and the NMOS region; forming a gate pattern comprising a floating gate electrode in the cell region and the peripheral region; and performing a junction ion implantation over a surface of the cell region, wherein the floating gate electrode has P-type conductivity. |
地址 |
Icheon-si Gyeonggi-do KR |