| 发明名称 |
ASPECT RATIO TRAPPING (ART) FOR FABRICATING VERTICAL SEMICONDUCTOR DEVICES |
| 摘要 |
Aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from are described. For example, a semiconductor device includes a substrate with an uppermost surface having a first lattice constant. A first source/drain region is disposed on the uppermost surface of the substrate and has a second, different, lattice constant. A vertical channel region is disposed on the first source/drain region. A second source/drain region is disposed on the vertical channel region. A gate stack is disposed on and completely surrounds a portion of the vertical channel region. |
| 申请公布号 |
US2017012125(A1) |
申请公布日期 |
2017.01.12 |
| 申请号 |
US201415119345 |
申请日期 |
2014.03.28 |
| 申请人 |
INTEL CORPORATION |
发明人 |
LE Van H.;CHU-KUNG Benjamin;DEWEY Gilbert;KAVALIEROS Jack T.;PILLARISETTY Ravi;RACHMADY Willy;RADOSAVLJEVIC Marko;METZ Matthew V.;MUKHERJEE Niloy;CHAU Robert S. |
| 分类号 |
H01L29/78;H01L29/423;H01L29/66;H01L29/786 |
主分类号 |
H01L29/78 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A semiconductor device, comprising:
a substrate with an uppermost surface having a first lattice constant; a first source/drain region disposed on the uppermost surface of the substrate and having a second, different, lattice constant; a vertical channel region disposed on the first source/drain region; a second source/drain region disposed on the vertical channel region; and a gate stack disposed on and completely surrounding a portion of the vertical channel region. |
| 地址 |
Santa Clara CA US |
