Sense amplifier with mini-gap architecture and parallel interconnect

摘要

A memory array structure includes: a plurality of array sections and a plurality of mini-gaps, wherein each mini-gap is disposed between two array sections of the plurality of array sections. Each mini-gap includes: a local write device, for providing a data signal in response to a write enable signal and a write data signal, the data signal for performing a write operation on a memory cell of an array section; and a local sensor, for outputting a data signal in response to an activation command and a read enable signal. The memory array further includes a control logic for providing the write enable and read enable signals, and at least one main sense amplifier, for providing the write data signal to the local write device, receiving the data signal from the local sensor, and amplifying the received data signal for providing a read data signal to output data lines.

主权项

1. A memory array structure, comprising:
a plurality of array sections, each array section comprising a plurality of memory cells; a plurality of mini-gaps, each mini-gap disposed between two array sections of the plurality of array sections and comprising:
a local write device, for providing a data signal in response to a received write enable signal and write data signal, the data signal for performing a write operation on a specific memory cell of an array section; anda local sensor, for outputting a data signal upon receiving an activation command and a read enable signal; a control logic, for providing the write enable signal and the read enable signal; and at least a first main sense amplifier, for providing the write data signal to the local write device, receiving the data signal from the local sensor, and amplifying the received data signal for providing a read data signal to output data lines.