Gate spacers and methods of forming same

摘要

An embodiment device includes a gate stack extending over a semiconductor substrate, a hard mask disposed on a top surface of the gate stack, and a low-k dielectric spacer on a side of the gate stack. A top of the low-k dielectric spacer is lower than an upper surface of the hard mask. The device further includes a contact electrically connected to a source/drain region adjacent the gate stack. The contact extends laterally over the low-k dielectric spacer, and a dielectric material is disposed between the contact and the low-k dielectric spacer. The dielectric material has a higher selectivity to etching than the low-k dielectric spacer.

主权项

1. A device comprising:
a gate stack extending over a semiconductor substrate; a hard mask disposed on a top surface of the gate stack; a pair of low-k dielectric spacers on opposing sides of the gate stack, wherein top surfaces of the pair of low-k dielectric spacers are lower than an upper surface of the hard mask; and a contact electrically connected to a source/drain region adjacent to the gate stack, wherein the contact extends laterally over a first low-k dielectric spacer of the pair of low-k dielectric spacers, the first low-k dielectric spacer opposing a second low-k dielectric spacer of the pair of low-k dielectric spacers, wherein a dielectric material of one or more dielectric layers over the first low-k dielectric spacer is disposed between the contact and the first low-k dielectric spacer, wherein top surfaces of one or more dielectric layers over the second low-k dielectric spacer are substantially coplanar with the upper surface of the hard mask, wherein top surfaces of the one or more dielectric layers over the first low-k dielectric spacer are below the upper surface of the hard mask, and wherein the dielectric material has a higher selectivity to etching than material of the first low-k dielectric spacer.