| 发明名称 |
Frequency scaled segmented scan chain for integrated circuits |
| 摘要 |
A scan chain may be formed throughout an integrated circuit in which the scan chain includes at least a first segment and a second segment. A first portion of a test pattern is scanned into the first segment by clocking a first scan cell of the first segment with an even clock while clocking a remainder of the plurality of scan cells in the first segment with an odd clock, in which the odd clock is out of phase with the even clock, in which the even clock and odd clock have a rate equal to a scan rate of the test pattern divided by an integer N. A second portion of the test pattern is scanned into the second segment by clocking the plurality of scan cells in the second segment with the odd clock, such that the second portion of the test pattern is not scanned into the first segment. |
| 申请公布号 |
US9535123(B2) |
申请公布日期 |
2017.01.03 |
| 申请号 |
US201514985699 |
申请日期 |
2015.12.31 |
| 申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
Mittal Rajesh Kumar;Pradeep Wilson;Singhal Vivek |
| 分类号 |
G01R31/3177;G01R31/28;G01R31/317;G01R31/44 |
主分类号 |
G01R31/3177 |
| 代理机构 |
|
代理人 |
Neerings Ronald O.;Cimino Frank D. |
| 主权项 |
1. A method for testing an integrated circuit, the method comprising:
forming a scan chain throughout the integrated circuit in which the scan chain includes at least a first segment and a second segment each having a plurality of scan cells; receiving a test pattern for the scan chain at a test port on the integrated circuit, in which the test pattern is synchronized to a scan clock having a first rate; scanning in a first portion of the test pattern from the test port into the first segment by clocking a first scan cell of the first segment with an even clock while docking a remainder of the plurality of scan cells in the first segment with an odd clock, in which the odd dock is out of phase with the even dock, in which the even dock and the odd clock have a second rate equal to the first rate divided by an integer N; coupling the second segment to the test port to receive the test pattern while bypassing the first segment during a first mode of operation; and scanning in a second portion of the test pattern from the test port into the second segment by clocking the plurality of scan cells in the second segment with the odd clock, such that the second portion of the test pattern is not scanned into the first segment. |
| 地址 |
Dallas TX US |
