发明名称 AN INTEGRATED CIRCUIT PACKAGE WITH A HIGH ASPECT RATIO INTERCONNECT SOLDERED TO A REDISTRIBUTION LAYER OF A DIE OR OF A SUBSTRATE AND CORRESPONDING MANUFACTURING METHOD
摘要 A package (e.g., wafer level package) (300, 1102) that includes a die (305), a redistribution portion (306) coupled to the die (305), a first high aspect ratio interconnect (308, 1150, 1152) coupled to the redistribution portion (306) of the package (300, 1102), where the first high aspect ratio interconnect (308, 1150, 1152) comprises a width to height ratio of about at least 1:2, and a first solder interconnect (380, 1130, 1132) coupled to the first high aspect ratio interconnect (308, 1150, 1152) and the redistribution portion (306). The package (1102) may be coupled to a printed circuit board (1108) by a second solder interconnect (1180, 1182) coupled to the first high aspect ratio interconnect (1150, 1152) and the printer circuit board (1108). In an alternative embodiment, a package (1600) comprises a die (1604), a plurality of solder balls (1606) coupled to the die (1604), a package substrate (1602) coupled to the die (1604) through the plurality of solder balls (1606), a first high aspect ratio interconnect (1608) coupled to the package substrate (1602), wherein the first high aspect ratio interconnect (1608) comprises a width to height ratio of about at least 1:2, and a first solder interconnect (1610) coupled to the first high aspect ratio interconnect (1608) and the package substrate (1602). The package may be coupled to a printed circuit board (1700) through the first high aspect ratio interconnect (1608), the high aspect ratio interconnect (1608) being coupled to an interconnect (e.g. pad) (1138) of the printed circuit board (1700) and a solder interconnect (1718). The first high aspect ratio interconnect (700, 900) may be a composite interconnect that includes a first conductive core (702, 902) and a first conductive layer (704, 904) that at least partially encapsulates the first conductive core (702, 902). The first conductive layer (704, 904) may be a diffusion barrier. The composite interconnect (900) may further comprise a second conductive layer (906) that at least partially encapsulates the first conductive layer (904). The second conductive layer (906) may include solder.
申请公布号 WO2016187593(A1) 申请公布日期 2016.11.24
申请号 WO2016US33643 申请日期 2016.05.20
申请人 QUALCOMM INCORPORATED 发明人 ALVARADO, Reynante Tamunan;KESER, Lizabeth Ann;CUI, Tong
分类号 H01L23/485;H01L21/60;H01L23/498;H05K3/34 主分类号 H01L23/485
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