| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock generating circuit for a sample-hold circuit, the clock generating circuit having a simple configuration and capable of reducing influence of noise.SOLUTION: A clock signal generating circuit for generating a clock signal of an intended frequency component from an input signal includes: a first filter having a peak of a gain in a frequency lower than an intended frequency; a second filter having a peak of the gain in a frequency higher than the intended frequency; first and second quantizing circuits connected to outputs of the first filter and the second filter respectively; and a synthesis circuit that is connected to the outputs of the first quantizing circuit and the second quantizing circuit, reverses the output of one quantizing circuit and synthesizes the output of the another quantizing circuit. This configuration can generate a sample-hold signal capable of inhibiting generation of a clock signal in an unnecessary frequency region so as to suppress superimposition on an envelope detection by an interfering frequency signal. |
