发明名称 |
Architecture for three dimensional non-volatile storage with vertical bit lines |
摘要 |
A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. |
申请公布号 |
EP2731108(B1) |
申请公布日期 |
2016.08.31 |
申请号 |
EP20140152902 |
申请日期 |
2011.12.12 |
申请人 |
SANDISK TECHNOLOGIES LLC |
发明人 |
SCHEUERLEIN, ROY, E. |
分类号 |
G11C13/00;G11C5/02;G11C8/08;H01L27/24;H01L45/00 |
主分类号 |
G11C13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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