发明名称 半導体集積回路装置及びその製造方法
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which further reduces resistivity of a wiring layer, and is excellent in electromigration resistance, and to provide a method for manufacturing the same.SOLUTION: The semiconductor integrated circuit device includes: a semiconductor substrate having a circuit element therein; an insulating layer formed on a main surface of the semiconductor substrate; a trench formed at least by using the insulating layer; and a copper wire formed in the trench. A line width of the copper wire is 70 nm or less, an average crystal grain diameter in a portion in a distance which is 1/4 of a distance between a bottom surface of the trench of the copper wire and a height of the trench is 1.3 times or more of the wire length, and a ratio of the average crystal grain diameter to the average crystal grain diameter of the surface of the uppermost part of the trench is 85% or more. The semiconductor integrated circuit device having such characteristics is manufactured by a cycle annealing treatment in which a maximum temperature is set at 450°C or higher or by electrolytic plating using a copper sulfate plating bath with a purity of more than 6 N and an anode copper electrode with a purity of more than 6 N.
申请公布号 JP5963191(B2) 申请公布日期 2016.08.03
申请号 JP20120124608 申请日期 2012.05.31
申请人 国立大学法人茨城大学 发明人 篠嶋 妥;大貫 仁;玉橋 邦裕
分类号 H01L21/3205;C25D5/50;C25D7/12;C25D17/10;H01L21/28;H01L21/288;H01L21/768;H01L23/532 主分类号 H01L21/3205
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