发明名称 低電力高速デジタル受信器
摘要 Described herein is a low power high-speed digital receiver. The apparatus of the receiver comprises: a sampling unit operable to sample a differential input signal and to boost input signal gain, the sampling unit to generate a sampled differential signal with boosted input signal gain; and a differential amplifier to amplify the sampled differential signal with boosted input signal gain, the differential amplifier to generate a differential amplified signal.
申请公布号 JP5937229(B2) 申请公布日期 2016.06.22
申请号 JP20140547170 申请日期 2011.12.21
申请人 インテル コーポレイション 发明人 ソーン,ホーンジアーン
分类号 H04L25/03;H04L25/02 主分类号 H04L25/03
代理机构 代理人
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