发明名称 RECEIVING CIRCUIT AND CONTROL METHOD THEREOF
摘要 PROBLEM TO BE SOLVED: To provide a receiving circuit capable of adjusting an edge of a clock to desired timing by correcting a duty ratio of the clock.SOLUTION: A receiving circuit 4 includes an acquisition circuit 7, a correction amount generation circuit 9, and a duty ratio correction circuit 121. The acquisition circuit 7 acquires data at each of a first edge of a first clock DCKA, a second edge of a second clock DCKAX, a third edge of a third clock DCKB, and a fourth edge of a fourth clock DCKBX, whose clocks have the same period. The correction amount generation circuit 9 generates correction amount from data acquired by each of the first edge to the fourth edge, so that the acquisition circuit 7 acquires data at desired timing with the first edge to the fourth edge. The duty ratio correction circuit 12 corrects duty ratios of the first clock DCKA to the fourth clock DCKBX in accordance with the correction amount.SELECTED DRAWING: Figure 2
申请公布号 JP2016103715(A) 申请公布日期 2016.06.02
申请号 JP20140240501 申请日期 2014.11.27
申请人 FUJITSU LTD 发明人 TOMITA YASUMOTO
分类号 H04L7/02 主分类号 H04L7/02
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