NON-PLANAR SEMICONDUCTOR DEVICE HAVING GROUP III-V MATERIAL ACTIVE REGION WITH MULTI-DIELECTRIC GATE STACK

摘要

Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body (206) with a channel region. A source and drain material region (226) is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack (220, 222, 224) is disposed in the trench and on the exposed portion of the channel region. The gate stack includes a first dielectric layer (220) on outer portions of the channel region (206), a second dielectric layer (222) on an inner portion of the channel region, and a gate electrode (224).