| 摘要 |
Provided is a semiconductor memory device which restrains a breakdown of a low-voltage transistor constituting a bit line selecting circuit. An NAND string unit (NU) and transistors (BLSe, BLso, BIASe, BIASo) that constitute the bit line selecting circuit are formed in a P-well. The transistors (BLSe, BLSo, BIASe, BIASo) are set in a floating state during erasing operation. The voltages of the transistors (BLSe, BLSo, BIASe, BIASo) are increased when an erasing voltage is applied to the P-well. When the erasing voltage is discharged from the P-well, gates of the transistors (BLSe, BLSo, BIASe, BIASo) are connected to a reference potential by a discharging circuit (410), and the gate voltage is discharged to follow the voltage of the P-well. |
