CLOCK GENERATOR

摘要

A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.

主权项

1. An integrated circuit, comprising:
a clock generator, for generating a continuous output clock signal, the clock generator comprising:
a first clock signal input, for receiving a first input clock signal; anda second clock signal input, for receiving a second input clock signal; at least one digital audio interface, for receiving digital audio data with an accompanying audio data clock; a digital-analog converter, for reconstructing analog audio data based on received digital audio data; wherein the audio data clock is provided to the clock generator as the first input clock signal, and the output clock signal of the clock generator is used as the clock for the digital-analog converter; and wherein the received digital audio data and accompanying audio data clock are received by the device in burst mode, and the digital-analog converter is continuously supplied with the output clock signal of the clock generator, and the output clock signal of the clock generator is based on the first input clock signal and the second input clock signal.