发明名称 |
REDUCING DIRECT SOURCE-TO-DRAIN TUNNELING IN FIELD EFFECT TRANSISTORS WITH LOW EFFECTIVE MASS CHANNELS |
摘要 |
An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact on a semiconductor substrate and forming a channel with a first channel layer on the first source/drain contact. The approach further includes forming the barrier on the first channel layer, and a second channel layer on the barrier followed by forming a second source/drain contact on the second channel layer. |
申请公布号 |
US2016149050(A1) |
申请公布日期 |
2016.05.26 |
申请号 |
US201514931930 |
申请日期 |
2015.11.04 |
申请人 |
International Business Machines Corporation |
发明人 |
Basu Anirban;Majumdar Amlan;Sleight Jeffrey W. |
分类号 |
H01L29/786;H01L29/423 |
主分类号 |
H01L29/786 |
代理机构 |
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代理人 |
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主权项 |
1. A semiconductor structure with a barrier for field effect transistors with low effective mass channel materials, comprising:
a semiconductor substrate; a first source/drain layer on the semiconductor substrate; a first channel layer on the first source/drain layer; a barrier layer on the first channel layer; a second channel layer on the barrier layer, wherein the barrier layer is composed of a first semiconductor material with a lower electron affinity than a semiconductor material of the first channel layer and the second channel layer in a n-type field effect transistor; and a second source/drain layer on the second channel layer; |
地址 |
Armonk NY US |