CHARGING AND DISCHARGING CONTROL CIRCUIT FOR BATTERY DEVICE

摘要

A source of a pass-on FET is connected to a charger (load) terminal node connected to a battery terminal, a drain of the pass-on FET is connected to a gate of the current-pass FET, a gate of the pass-on FET is connected to a first control signal of a controller, a drain of the current-pass FET is connected to the other terminal of a battery, and a source of the current-pass FET is connected to one terminal of a charger. Two pass-off FETs are connected in series between the drain and the gate of the current-pass FET, one of gates of the two pass-off FETs is connected to a second control signal outputted from the controller, the other one of the gates of the two pass-off FETs is connected to a level converter, and an input of the level converter is connected to the second control signal.

主权项

1. A charging and discharging control circuit which operates in response to a charging and discharging control signal of a battery, comprising:
a charger (load) terminal node connected to a terminal of a battery; a level converter; a controller which generates a first control signal, a second control signal and a third control signal; and a first FET, a second FET, a third FET, a fourth FET, a fifth FET and a sixth FET, wherein the source and drain of the first FET are connected between the terminal node and the gate of the sixth FET, and the gate of the first FET is connected to the first control signal, and the drain (source) of the sixth FET is connected to the other terminal of the battery, and the source (drain) of the sixth FET is connected to the other terminal of the charger (load), and the drain and source of the second FET and the drain and source of the third FET are connected between the gate and drain (source) of the sixth FET, and the drain and source of the fourth FET and the drain and source of the fifth FET are connected between the gate and drain (source) of the sixth FET, and the gate of the fourth FET receives the third control signal, and the gate of the fifth FET receives the third control signal, and the gate of the second FET receives the second control signal, and the gate of the third FET receives the second control signal, and the level converter is connected between one between the gate of the second FET and the gate of the third FET and the second control signal.