发明名称 |
Increasing communication safety by preventing false packet acceptance in high-speed links |
摘要 |
Methods, apparatus, and systems for preventing false packet acceptance in high-speed links. Under one aspect, correctable symbol errors are detected, and determination is made to whether a symbol error rate or ratio (SER) exceeds an SER threshold. In response to detection of such a condition, the link is disconnected or temporarily paused. The value for the SER threshold is determined using a statistical analysis of various link parameters to meet desired performance levels, such as a mean time to false packet acceptance (MTTFPA) of >approximately 15 billion years while providing a mean time to disconnect of >100 years. |
申请公布号 |
US9344219(B2) |
申请公布日期 |
2016.05.17 |
申请号 |
US201313926041 |
申请日期 |
2013.06.25 |
申请人 |
Intel Corporation |
发明人 |
Ran Adee O. |
分类号 |
H03M13/00;H04L1/00;H04L1/20;H04L1/24 |
主分类号 |
H03M13/00 |
代理机构 |
Law Office of R. Alan Burnett, P.S |
代理人 |
Law Office of R. Alan Burnett, P.S |
主权项 |
1. A method, comprising:
detecting a correctable symbol error ratio (SER) for a high-speed link which employs forward error correction (FEC); and disconnecting or temporarily pausing the high-speed link if the correctable SER exceeds a predetermined threshold, wherein the high-speed link couples a pair of link partners in communication and includes four Forward Error Correction (FEC) lanes, and each link partner includes a Physical (PHY) interface including a Reed-Solomon Forward Error Correction (RS-FEC) sublayer, and wherein detecting the correctable SER comprises employing a Reed-Solomon decoder in the RS-FEC sublayer to count a number of correctable symbol errors detected on the four FEC lanes of in consecutive non-overlapping blocks of 8192 codewords. |
地址 |
Santa Clara CA US |