发明名称 |
Scan test circuit, test pattern generation control circuit, and scan test control method |
摘要 |
A scan test generation method includes dividing a single clock domain into a plurality of regions; incorporating a test pattern generation control circuit in each of the regions; selecting one of a skewed-load mode and a broadside mode as a test pattern generation mode by the test pattern generation control circuit for each region; generating a test pattern determined based on selected one of the test pattern generation mode for each region; and generating a test pattern such that the skewed-load mode and the broadside mode are mixed in a single clock domain. |
申请公布号 |
US9341674(B2) |
申请公布日期 |
2016.05.17 |
申请号 |
US201514733814 |
申请日期 |
2015.06.08 |
申请人 |
RENESAS ELECTRONICS CORPORATION |
发明人 |
Yonetoku Hirofumi;Yamada Norihiro |
分类号 |
G01R31/3177;G01R31/3185 |
主分类号 |
G01R31/3177 |
代理机构 |
McGinn IP Law Group, PLLC |
代理人 |
McGinn IP Law Group, PLLC |
主权项 |
1. A scan test generation method comprising:
dividing a single clock domain into a plurality of regions; incorporating a test pattern generation control circuit in each of the regions; selecting one of a skewed-load mode and a broadside mode as a test pattern generation mode by the test pattern generation control circuit for each region; generating a test pattern determined based on a selected one of the test pattern generation mode for each region; and generating a test pattern such that the skewed-load mode and the broadside mode are mixed in a single clock domain. |
地址 |
Kawasaki-Shi, Kanagawa JP |