发明名称 INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
摘要 A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.
申请公布号 US2016133632(A1) 申请公布日期 2016.05.12
申请号 US201514853442 申请日期 2015.09.14
申请人 PARK Hong-bae;KU Ja-hum;KIM Myeong-cheol;LEE Jin-wook;HAN Sung-kee 发明人 PARK Hong-bae;KU Ja-hum;KIM Myeong-cheol;LEE Jin-wook;HAN Sung-kee
分类号 H01L27/11;H01L27/02;H01L27/092 主分类号 H01L27/11
代理机构 代理人
主权项 1. An integrated circuit device comprising: a plurality of active regions formed on a substrate and extending in a first direction; a first gate line and a second gate line formed on the substrate, extending in a straight line in a second direction and crossing the plurality of active regions, wherein the first gate line and the second gate line are spaced apart from each other; a first gate insulation layer extending in the second direction and covering a first surface of the first gate line facing a portion of the plurality of active regions and a first long-axis sidewall of the first gate line, while not covering a first short-axis sidewall of the first gate line facing the second gate line; a second gate insulation layer extending in the second direction and covering a second surface of the second gate line facing another portion of the plurality of active regions and a second long-axis sidewall of the second gate line, while not covering a second short-axis sidewall of the second gate line facing the first gate line; and an inter-gate insulation region interposed between the first gate line and the second gate line and abutting the first short-axis sidewall and the second short-axis sidewall.
地址 Seoul KR