THERMAL TREATED SEMICONDUCTOR/GATE DIELECTRIC INTERFACE FOR GROUP IIIA-N DEVICES

摘要

In described examples, a method (100) of fabricating a gate stack for a power transistor device includes thermally oxidizing (101) a surface of a Group IIIA-N layer on a substrate to form a first dielectric layer of an oxide material that is > 5A thick. A second dielectric layer being silicon nitride or silicon oxynitride is deposited (102) on the first dielectric layer. A metal gate electrode is formed (104) on the second dielectric layer.