Dynamic random access memory cell employing trenches located between lengthwise edges of semiconductor fins

摘要

After formation of semiconductor fins in an upper portion of a bulk semiconductor substrate, a shallow trench isolation layer is formed, which includes a dielectric material and laterally surround lower portions of each semiconductor fin. Trenches are formed between lengthwise sidewalls of neighboring pairs of semiconductor fins. Portions of the shallow trench isolation layer laterally surrounding each trench provide electrical isolation between the buried plate and access transistors. A strap structure can be formed by etching a via cavity overlying a portion of each trench and a source region of the corresponding access transistor, and filling the via cavity with a conductive material. A trench top oxide structure electrically isolates an inner electrode of each trench capacitor from an overlying gate line for the access fin field effect transistor.

主权项

1. A semiconductor structure comprising:
semiconductor fins located on a substrate; and a trench capacitor located within said substrate, wherein an entirety of a node dielectric of said trench capacitor is located between a first vertical plane including a proximal lengthwise sidewall of a first semiconductor fin within a neighboring pair of said semiconductor fins and a second vertical plane including a proximal lengthwise sidewall of a second semiconductor fin within said neighboring pair of said semiconductor fins.