发明名称 Variable Frequency Charge Pump
摘要 A charge pump circuit that utilizes a sensing circuit for determining the current loading or status of the output supply generated by the charge pump circuit to determine a corresponding frequency for a variable rate clock for the charge pump circuit. When a current load is present, the clock frequency automatically ramps up to a relatively high level to increase the output current of the charge pump circuit. When the current load is removed and the supply is settled out, the clock frequency is automatically reduced to a relatively quieter level and the charge pump circuitry operates at a lower power level. Accordingly, the charge pump circuit is only noisy when it has to be, thus providing optimal power when required and being electrically quiet and operating at lower power at all other times.
申请公布号 US2016126835(A1) 申请公布日期 2016.05.05
申请号 US201614991577 申请日期 2016.01.08
申请人 Peregrine Semiconductor Corporation 发明人 Englekirk Robert Mark
分类号 H02M3/07 主分类号 H02M3/07
代理机构 代理人
主权项 1. A variable frequency charge pump circuit, including: (a) a charge pump having a clock signal input, a voltage supply input, and an output, for providing a pumped output voltage at the output based on a regulated input voltage applied at the voltage supply input, with a current available at the output as a function of the frequency of a signal applied to the clock signal input; (b) a feedback circuit coupled to the charge pump output for providing a feedback signal indicative of the pumped output voltage at such output; (c) a voltage regulator coupled to a voltage source, the charge pump voltage supply input, and the feedback circuit, for providing a regulated input voltage to the charge pump voltage supply input in response to the feedback signal, thereby regulating the pumped output voltage at the charge pump output, the voltage regulator including: (1) a controllable conductivity device coupled to the voltage source and to the charge pump voltage supply input, and having a control input for controlling the conductivity of the controllable conductivity device; and(2) an amplifier having an output coupled to the control input of the controllable conductivity device, a first input coupled to a reference voltage, and a second input coupled to the feedback circuit, for generating a control signal at the amplifier output that varies as a function of a difference between the feedback signal and the reference voltage, the control signal controlling the conductivity of the controllable conductivity device and thus the input voltage applied to the charge pump voltage supply input; (d) a clock source having a voltage input coupled to the voltage source, a control input configured to receive a bias signal generated from the control signal from the amplifier output, and a clock signal output coupled to the charge pump clock signal input, for generating a clock signal at the clock signal output coupled to the charge pump clock signal input, the clock signal having a frequency that is a function of the control signal, thereby controlling the amount of current available to a load coupled to the charge pump output as a function of the frequency of the clock signal, whereby as the load increases, the frequency of the clock signal increases and the current available from the charge pump output increases, and as the load decreases, the frequency of the clock signal decreases and the current available from the charge pump output decreases.
地址 San Diego CA US