SOC design with critical technology pitch alignment

摘要

An SOC apparatus includes a plurality of gate interconnects with a minimum pitch g, a plurality of metal interconnects with a minimum pitch m, and a plurality of vias interconnecting the gate interconnects and the metal interconnects. The vias have a minimum pitch v. The values m, g, and v are such that g2+m2≧v2 and an LCM of g and m is less than 20 g. The SOC apparatus may further include a second plurality of metal interconnects with a minimum pitch of m2, where m2>m and the LCM of g, m, and m2 is less than 20 g.

主权项

1. A system on a chip (SOC) apparatus, comprising:
a plurality of gate interconnects with a minimum pitch g; a plurality of metal interconnects with a minimum pitch m; and a plurality of vias formed in a single patterning process for a manufacturing technology less than or equal to 20 nm and interconnecting the gate interconnects and the metal interconnects, the vias having a minimum pitch v, wherein g2+m2≧v2, wherein the minimum pitch v is greater than the minimum pitch g and the minimum pitch m used in the apparatus and a least common multiplier (LCM) of g and m is less than 20 g, wherein the parameters g and m are in nm.