Forward error correction decoder and method therefor

摘要

A Forward Error Correction (FEC) decoder is provided, for example including a Layered Low Density Parity Check (LDPC) component. In an implementation, power consumption of the LDPC decoder is minimized with minimal to no impact on the error correction performance. This is achieved, in an implementation, by partially or fully eliminating redundant operations in the iterative process.

主权项

1. An iterative forward error correction (FEC) decoder configured to perform a set of decoding operations during a selected FEC decode, comprising:
a main memory configured to receive an input and to transmit an output; a plurality of check node convergence testers; a plurality of layer processors, each layer processor comprising:
a check node configured to receive a signal based on the main memory output, and to process the received signal based on a message passing method; anda unique check node convergence tester, from among the plurality of check node convergence testers, configured to test for convergence on the check node;wherein the layer processor performs only a subset of the set of decoding operations of the layer processor in response to a determination that the check node of the layer processor has converged; wherein the plurality of check node convergence testers is equal in number to the plurality of layer processors; an adder in communication with the check node and configured to receive a check node output to combine extrinsic information generated by the check node with channel information for the layer and provide the combined information to the main memory for storage for an update; and a delay element configured to feed back the extrinsic information from the check node output for processing in the next iteration; wherein the check node convergence tester is configured to disable a write-back operation to the delay element when the check node has converged.