Electrical Connections for Chip Scale Packaging

摘要

Electrical connections for chip scale packaging are disclosed. In one embodiment, a semiconductor device includes a post-passivation layer disposed over a substrate, the substrate having a first direction of coefficient of thermal expansion mismatch. The semiconductor device includes a first opening through the post-passivation layer, the first opening comprising a plurality of elongated apertures. A longest of the plurality of elongated apertures comprises a first dimension, wherein the first dimension is aligned substantially perpendicular to the first direction of coefficient of thermal expansion mismatch.

主权项

1. A device comprising:
a substrate having a center region and having peripheral regions; a conductive line on the substrate; and a passivation layer formed on the conductive line, the passivation layer having a plurality of apertures exposing respective regions of the conductive line, a longest one of the plurality of apertures having a major axis extending in a direction along a major plane of the substrate, the direction being substantially perpendicular to a stress vector, the stress vector caused by a difference in a respective coefficients of thermal expansion between at least two materials on the substrate.