Memory column drowsy control

摘要

In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column.

主权项

1. Apparatus comprising:
a memory array comprising a plurality of memory cells organized according to a plurality of rows and a plurality of columns; and a control row comprising a plurality of power control memory cells for controlling power provided to the memory array, the plurality of power control memory cells organized according to the plurality of columns, wherein the plurality of power control memory cells store power control data to select a full voltage level for a weak column of the plurality of memory cells, wherein the weak column includes at least one weak memory cell incapable of memory retention at a reduced voltage level, and the power control memory cells store power control data to select the reduced voltage level for a normal column of the plurality of memory cells, wherein the normal column consists of normal memory cells capable of memory retention at the reduced voltage level.