发明名称 半導体記憶装置
摘要 According to one embodiment, a semiconductor storage device includes multiple memory cells that include a variable resistance element and a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured so that, during the set operation in which the variable resistance element is changed to the set state, a set voltage of a first polarity is applied to the select memory cell. The control circuit is configured so that, during the reset operation in which the variable resistance elements are changed to the reset state, and a cancel voltage of the first polarity is applied to an unselected memory cell to which voltage that is less than the reset voltage was applied. The voltage value and the voltage application time of the set voltage and the voltage value and the voltage application time of the cancel voltage have a set relationship.
申请公布号 JP5902113(B2) 申请公布日期 2016.04.13
申请号 JP20130049934 申请日期 2013.03.13
申请人 株式会社東芝 发明人 市原 玲華
分类号 G11C13/00 主分类号 G11C13/00
代理机构 代理人
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