发明名称 |
Input buffer for semiconductor memory device and flash memory device including the same |
摘要 |
An input buffer includes an amplifier circuit configured to amplify an input signal and output an amplified signal to a first output node. The input signal is amplified according to a first bias voltage set, at a bias node, to a first level based on a power supply voltage and a reference voltage. The input buffer includes an output circuit configured to receive and buffer the amplified signal and output an output signal to a second output node. The input buffer includes a dynamic bias voltage generator configured to change the first bias voltage to a second level in response to a transition of the output signal. |
申请公布号 |
US9311973(B2) |
申请公布日期 |
2016.04.12 |
申请号 |
US201414558212 |
申请日期 |
2014.12.02 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
Kang Kyoung-tae |
分类号 |
G11C7/22;G11C16/10;H03K5/02;H03K19/0185;G11C16/08;G11C16/30;G11C5/14;G11C7/06;G11C7/10;H03F1/02;G11C29/02 |
主分类号 |
G11C7/22 |
代理机构 |
Harness, Dickey & Pierce, P.L.C. |
代理人 |
Harness, Dickey & Pierce, P.L.C. |
主权项 |
1. An input buffer, comprising:
an amplifier circuit configured to amplify an input signal and output an amplified signal to a first output node, the input signal being amplified according to a first bias voltage set, at a bias node, to a first level based on a power supply voltage and a reference voltage; an output circuit configured to receive and buffer the amplified signal and output an output signal to a second output node; and a dynamic bias voltage generator configured to change the first bias voltage to a second level in response to a transition of the output signal. |
地址 |
Gyeonggi-Do KR |